Overview

This document specifies what is and how should look Project Hardware (Hardware) used with Swart Service (Service).

Hardware describes cpu resources used in client’s project. The client is obligate to provide Hardware and to follow the rules how to define it explained in this document, if he wants to use Service.

General Hardware rules

• Hardware should contain only resources relative data and nothing else
• Hardware should be encoded with UTF8 settings
• Every resource should be in a separate row
• There should be no empty space between rows
• Hardware should be saved as text file (for example: .txt on Windows OS)

Resource rules

• Every resource must contain following fields (next to them is a field’s value requirement type):
  • core – mandatory
  • type – mandatory
  • name – mandatory
  • value – mandatory
  • reserved – mandatory if type is RAM or ROM, otherwise optional
  • cached – mandatory if type is RAM or ROM, otherwise optional
  • alias – mandatory if type is RAM or ROM, otherwise optional
• Between properties should be always separator character (client can define one)
• Separator can not be a letter or a number
• If the separator character is not specified, empty space “ “ will be used as separator
• Every property value must be enclosed with quotation mark

Resource’s properties

core – defines resource’s core number

type – type of the resource

name – represents a resource’s name

value – resource’s value

reserved – defines if memory is reserved

cached – defines if memory is cached

alias – defines another memory range for already defined resource

Properties Rules

core :

• only numbers
• starting from 0 .. N (N+1 core cpu)

type :

• only predefined values allowed: description, ram, rom

name :

• only letters, numbers, underscore allowed for characters

value :

• range with start/end pair in hexadecimal form
• start/end values separated using “;” separator
• if type is description every char is allowed

reserved :

• boolean value, true or false

cached :

• boolean value, true or false

alias :

• boolean value, true or false

Additional Resources (type description)

There are additional resources used to better define Hardware. They have description for type, and name, value pairs are as follows:

• MCU – MCU name – String value
• IVT – Interrupt Vector Table entry address – 1..N addresses in hexadecimal form, separated with ‘;’ separator
• IVTOFFSET – Offset in bytes for Interrupt Vector in Interrupt Vector Table – hexadecimal format, mandatory if IVT is defined
• IVTSIZE – Size of Interrupt Vector Table – size in bytes, hex format, mandatory if IVT is defined
• TVT -Trap Vector Table entry address – 1..N addresses in hexadecimal form, separated with ‘;’ separator
• TVTOFFSET – Offset in bytes for Trap Vector in Trap Vector Table – hexadecimal format, mandatory if TVT is defined
• TVTSIZE – size of Trap Vector Table – size in bytes, hex format, mandatory if TVT is defined
• INTERFACE – Interface name with type separated with ‘;’ separator. Interface type can be R – receiver or S – sender. String value
• RETURNVALUEREGISTER – Number of Data register used for return value from function
• RETURNADDRESSREGISTER – Number of Address register used for return pointers
• IFACERECEIVERRETNCVALUE – Return not connected value for Receiver interface
• IFACESENDERRETNCVALUE – Return not connected value for Sender interface

Example

core="0" type="RAM" name="DSPR0" value="0x70000000;0x7003BFFF" reserved="false" cached="false" alias="false"
core="0" type="RAM" name="PSPR0" value="0x70100000;0x7010FFFF" reserved="false" cached="false" alias="false"
core="0" type="RAM" name="DLMU0" value="0x90000000;0x9000FFFF" reserved="false" cached="false" alias="false"
core="0" type="RAM" name="DAM0" value="0x90400000;0x90407FFF" reserved="false" cached="false" alias="false"
core="0" type="RAM" name="DAM0" value="0xB0400000;0xB0407FFF" reserved="false" cached="false" alias="false"
core="1" type="RAM" name="DSPR1" value="0x60000000;0x6003BFFF" reserved="false" cached="false" alias="false"
core="1" type="RAM" name="DCACHE1" value="0x6003C000;0x6003FFFF" reserved="false" cached="false" alias="false"
core="1" type="RAM" name="PSPR1" value="0x60100000;0x6010FFFF" reserved="false" cached="false" alias="false"
core="1" type="RAM" name="DLMU1" value="0x90010000;0x9001FFFF" reserved="false" cached="false" alias="false"
core="1" type="RAM" name="DLMU1" value="0xB0010000;0xB001FFFF" reserved="false" cached="false" alias="false"
core="2" type="RAM" name="PSPR2" value="0x50100000;0x5010FFFF" reserved="false" cached="false" alias="false"
core="2" type="RAM" name="DLMU2" value="0x90020000;0x9002FFFF" reserved="false" cached="false" alias="false"
core="2" type="RAM" name="DLMU2" value="0xB0020000;0xB002FFFF" reserved="false" cached="false" alias="false"
core="0" type="ROM" name="PFL0" value="0x8010C000;0x802FFFFF" reserved="false" cached="false" alias="false"
core="1" type="ROM" name="PFL1" value="0x80300000;0x805FFFFF" reserved="false" cached="false" alias="false"
core="012" type="DESCRIPTION" name="MCU" value="TC377"
core="012" type="DESCRIPTION" name="IVT" value="0x8010C100;0x8010C400"
core="012" type="DESCRIPTION" name="IVTOFFSET" value="0x20"
core="012" type="DESCRIPTION" name="IVTSIZE" value="0x1000"
core="0" type="DESCRIPTION" name="TVT" value="0x8010FB00"
core="0" type="DESCRIPTION" name="TVTOFFSET" value="0x20"
core="0" type="DESCRIPTION" name="TVTSIZE" value="0x1000"
core="012" type="DESCRIPTION" name="INTERFACE" value="Rte_Write_CtApHCA_PpLDW_DLC_LDW_DLC;S"
core="012" type="DESCRIPTION" name="RETURNVALUEREGISTER" value="2"
core="012" type="DESCRIPTION" name="RETURNADDRESSREGISTER" value="2"
core="012" type="DESCRIPTION" name="IFACERECEIVERRETNCVALUE" value="134"
core="012" type="DESCRIPTION" name="IFACESENDERRETNCVALUE" value="0"